1. Field of the Invention
The present invention relates to a highly integrated read-only memory (ROM) which is at a low cost, and a method of fabricating the same.
2. Background of the Invention
In a mask ROM which is a nonvolatile memory, data are written in response to masking patterns in a stage of fabrication and a basic structure of each memory cell is formed by a 1-bit single transistor, whereby an occupied area per bit is small as compared with other reloadable memories. Thus, the mask ROM is suitable for mass storage and mass production. Through such characteristics, short delivery is strongly required in a mask ROM applied field of office automation products and games handling large quantities of fixed data in relation to implementation of mass storage, increase in speed and production cycles for attaining high function and high performance of products, and development has been made in order to cope with such requirement.
At present, 8-megabit memories are now in full-scale mass production, followed by 16-megabit ones. Further, 32-megabit memories are now reaching the end of development. In consideration of memory cell sizes, operating speeds and TAT (turn around time), memory cells of mask ROMS having basic structures of 1-bit single transistors are classified into two types including those of a NOR type flat memory cell system (first prior art) shown in FIG. 40 and a NAND type system (second prior art) shown in FIG. 43 in currently available 2-megabit mass storage ROMs or those of larger capacity.
[First Prior Art]
In the first prior art of the NOR type fiat memory cell shown in FIGS. 40 to 42, N.sup.+ -type diffusion layers 1 for defining bit lines are formed and thereafter polycide gates 2 are formed to be perpendicular thereto as shown in FIGS. 40 to 42, in order to reduce a contact number per bit (contactless structure) thereby remarkably reducing memory cell areas and increasing the degree of integration. As to respective memory cells, intersections between the polycide gates 2 and the N.sup.+ -type diffusion layers 1 define sources/drains 3, and channels (active regions) 4 are formed in space portions between approximate pairs of the sources/drains 3. In such a structure, gate lengths of the respective memory cells are defined by space lengths between approximate N.sup.+ -type diffusion layers 1, while gate widths are defined by widths of the polycide gates 2. In the first prior art, a data writing operation (impurity implantation for programming) is carried out after formation of gate electrodes, whereby it is possible to cope with any data writing in relatively short delivery, so far as memory cell intermediate products after formation of the gate electrodes are prepared.
[Second Prior Art]
The second prior art shown in FIGS. 43 to 45 is a NAND type ROM. Referring to FIGS. 43 to 45, numeral 11 denotes N.sup.+ -type diffusion layers for defining bit lines, numeral 12 denotes polycide gates for defining word lines, numeral 13 denotes sources/drains, and numeral 14 denotes channels. In the second prior art, a plurality of memory cells are vertically stacked to form NAND with respect to the N.sup.+ -type diffusion layers 11 (bit lines), gate lengths are reduced by fine working and a process technique, and the memory cells are stacked by 16 stages, to improve the degree of integration. Since the memory cells are stacked by 16 stages with respect to the N.sup.+ -type diffusion layers 11 (bit lines), read currents for the memory cells are so small that it is necessary to devise the circuit design in order to attain a high speed and a low voltage. In the second embodiment, a data writing step is carried out before formation of the polycide gates 12, whereby the number of steps following the data writing step is increased and hence it is difficult to cope with short delivery as compared with the first prior art.
[Third Prior Art]
FIG. 46 is a plan view schematically showing a semiconductor memory device (sequential access memory) according to third prior art. Referring to FIG. 46, symbol WL denotes a word line, symbol BL denotes a bit line, symbol DXc denotes an X address decoder for decoding the word line WL, symbol DYc denotes a Y address decoder for decoding the bit line BL, symbol Dc denotes elements for selecting the word line WL or the bit line BL in the respective address decoders DXc and DYc, and symbol PL denotes a predecoding line. FIG. 47 is a circuit diagram schematically showing a portion around a decoder part of the semiconductor memory device according to the third prior art. Referring to FIG. 47, symbols Dc01, Dc02, . . . denote decoder parts, symbols Pd01, . . . denote predecoder parts, symbols PL01, PL02 and PL03 denote predecoding lines, symbol Cnt denotes a counter, symbol L.alpha. denotes wires coupling the decoder parts Dc01, Dc02, . . . , with the predecoding lines PL01, PL02 and PL03.
According to the third prior art, outputs of the counter Cnt are decoded in two stages by the predecoder parts Pd01, . . . and the decoder parts Dc01, Dc02, . . . , to select any of the memory cells which are connected to the bit line BL and the word line WL, as shown in FIG. 47. Namely, signals which are once decoded by the predecoder parts Pd01, . . . are passed through the predecoding lines PL01, PL02 and PL03 along the direction X (word line WL) and the direction Y (bit line BL) of the memory cell array and again decoded by the X and Y address decoders DXc and DYc respectively as shown in FIG. 47, so that selection signals are finally transmitted to the word line WL and the bit line BL. According to the third prior art, the word line WL, the bit line BL and the predecoding lines PL01, PL02 and PL03 are connected with each other in a multiple bus system, with the plurality of predecoding lines PL01, PL02 and PL03 serving as bus bars.
[Fourth Prior Art]
FIG. 52 schematically shows a general memory cell array. In general, a transverse stage of blocks are selected in data reading. Referring to FIG. 52, a stage of blocks (0, 0), (1, 0), . . . are selected for data reading, for example. FIG. 53 shows a block structure of a memory cell array according to fourth prior art, and FIG. 54 shows a reference circuit (reference transistor array) structure for setting reference values for deciding types of memory cells. Referring to FIG. 53, symbols m0 to m7 denote memory cell transistors, symbols n0 to n9 denote nodes which are connected to respective sources/drains of the memory cell transistors m0 to m7, symbols m8 to m17 denote block selecting transistors, numeral 201 denotes a main bit line of aluminum or the like, numeral 202 denotes a virtual GND line of aluminum or the like, numeral 203 denotes local bit lines consisting of diffusion layers, symbol BWL0 denotes a block selecting word line which is gate-inputted in the block selecting transistors m8 to m12, symbol BWL1 denotes a block selecting word line which is gate-inputted in the block selecting transistors m13 to m17 similarly to the above, and symbols SWL0 to SWLn denote switching word lines for selecting the respective memory cell transistors. Referring to FIG. 54, symbol MA denotes a memory cell array, symbol SA denotes a differential sense amplifier, and symbol RA denotes a reference transistor mini array.
When data is read from the memory cell transistor m5 in FIG. 53, the word line BWL0 is set at a high level, the word line BWL1 is set at a low level, the word line SWLn is set at a high level and the remaining word lines SWL are set at low levels. Considering a current path between the main bit line 201 and the virtual GND line 202, a current flows from (1) the main bit line 201 through (2) the block selecting transistor m10, (3) the node n7, (4) the memory cell transistor m5, (5) the node n6 and (6) the block selecting transistor m9 in (7) the virtual GND line 202. According to the fourth prior art, the reference transistor mini array RA is arranged in the exterior of the memory cell array MA.
[Problems of First Prior Art and Second Prior Art]
In each of the first prior art and the second prior art described above, a determination is made as to whether data is "0" or "1" depending on whether or not a current flows to a single memory cell for data reading, i.e., across a source and a drain of a single transistor, as shown in FIG. 48. In other words, a single memory cell corresponds to 1-bit data in the conventional memory. Referring to FIG. 48, (0) denotes a memory cell which is not fed with a current in a turn-on time, and (i) denotes a memory cell which is fed with a current in a turn-on time respectively.
In such a structure, however, reduction in chip size of a ROM is limited. Particularly in a 32-megabit ROM, for example, about 90% of the chip area is occupied with a memory cell array. In order to remarkably reduce the chip size in the same degree of refinement, i.e., to improve the degree of data integration in the same area as the prior art, it is necessary to change the structure of the memory cell itself.
[Problem of Fourth Prior Art]
Also in the fourth prior art, a determination is made as to whether data is "0" or "1" depending on whether or not a current flows to a single memory cell for data reading, similarly to the first or second prior art. In order to implement a mass storage ROM in such a structure, the fabrication process must be refined to remarkably reduce the chip size, similarly to the first or second prior art.
Consider that data is read from the memory cell m5 in the fourth prior art, for example. In this case, the word lines BWL0 and SWLn are set at high levels and the remaining word lines SWL0, . . . and BWL1 are set at low levels, to select the memory cell m5.
At this time, a current path is formed between the main bit line 201 and the virtual GND line 202 along the main bit line 201.fwdarw.m10.fwdarw.n7.fwdarw.m5.fwdarw.n6.fwdarw.m9.fwdarw.the virtual GND line 202.
When the transistor m6 is in an ON state, a path is formed from the main bit line 201 along m11.fwdarw.n8.fwdarw.m6.fwdarw.n7. When the transistor m4 is in an 0N state, on the other hand, a path is formed along n6.fwdarw.m4.fwdarw.n5.fwdarw.m8.fwdarw.the virtual GND line 202. Thus, the resistance value of the overall system between the main bit line 201 and the virtual GND line 202 extremely depends on whether the transistors m4 and m6 adjacent to the target memory cell m5 are programmed in ON or OFF states in the fourth prior art, and a virtual ON-state current value of the memory cell fluctuates in response. Thus, current errors are caused when reference is made on the memory cell data by a reference circuit which is provided in the exterior of the memory cell array.
[Problem of Third Prior Art]
In the semiconductor memory device according to the third prior art which drives the predecoding lines PL (PL01, PL02 and PL03) of the same lengths as the memory cell array as shown in FIG. 47, the decoder parts Dc01, Dc02, . . . are required in the same number as that of the word line WL and the bit line BL. Therefore, the predecoding lines PL (PL01, PL02 and PL03) are so lengthened with increase in storage capacity that lengths Wx and Wy appearing in FIG. 46 are increased to increase the areas of the address decoders DXc and DYc. Referring to FIG. 47, the number of the predecoder parts Pd01, . . . is limited to three and the data from the counter Cnt are limited to two bits, whereby only four wires are required in each of the predecoding lines PL01, PL02 and PL03, to require 12 wires as a whole. As shown in FIG. 47, the number of the wires L.alpha. coupling the decoder parts Dc01, Dc02, . . . with the predecoding lines PL01, PL02 and PL03 is 2.sup.6 due to the multiple bus system. However, when this structure is applied to about 16 mega (2.sup.24) bits or the like in practice, for example, 28 wires are required for the overall predecoding lines PL. Further, the number of the wires L.alpha. is about 2.sup.11 for the X address decoder DXc and about 2.sup.13 for the Y address decoder DYc, and hence the length of each of the predecoder lines PL01, PL02 and PL03 must inevitably be increased. Due to such increase in length of the predecoding lines PL (PL01, PL02 and PL03), the processing speed is reduced and power consumption is increased. Further, the cost for the chip is increased due to increase of the area.